ASIC Design Verification Engineer
Cerebras is developing a radically new chip and system to dramatically accelerate deep learning applications. Our system runs training and inference workloads orders of magnitude faster than contemporary machines, fundamentally changing the way ML researchers work and pursue AI innovation.
We are innovating at every level of the stack – from chip, to microcode, to power delivery and cooling, to new algorithms and network architectures at the cutting edge of ML research. Our fully-integrated system delivers unprecedented performance because it is built from the ground up for deep learning workloads.
Cerebras is building a team of exceptional people to work together on big problems. Join us!
- Work with RTL designers and software engineers to ensure a high quality design that works first silicon.
- Develop detailed test and coverage plans based on the micro-architecture.
- Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage.
- Write tests, manage regressions, gather coverage, and debug test failures.
Skills & Qualifications
- Great debugging and problem solving skills.
- Deep knowledge of SystemVerilog testbench language, DPI, and UVM.
- Excellent programming skills and knowledge of software engineering practices including object-oriented design.
- Experience developing scalable and portable testbenches and components.
- Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations.
- Proficient in a scripting language such as Python or Perl.
- 5 years of Design Verification experience.
- Knowledge of pipelined processor architecture.
- Experience in writing reference models in C++.
- BS or MS in Computer Science or Electrical Engineering.
Our cozy and well-appointed headquarters are in the heart of Silicon Valley near downtown Los Altos, California.