Design For Testability (DFT) Engineer

Cerebras is developing a radically new chip and system to dramatically accelerate deep learning applications. Our system runs training and inference workloads orders of magnitude faster than contemporary machines, fundamentally changing the way ML researchers work and pursue AI innovation.

We are innovating at every level of the stack – from chip, to microcode, to power delivery and cooling, to new algorithms and network architectures at the cutting edge of ML research. Our fully-integrated system delivers unprecedented performance because it is built from the ground up for deep learning workloads. The system is fed with a high performance I/O subsystem based on the latest industry standard network protocols.

Cerebras is building a team of exceptional people to work together on big problems. Join us!

Responsibilities of the DFT Engineer:

  1. Generate, evaluate and own ATPG and DFT tool flow.
  2. Generate ATPG patterns, create/run/debug gate and SDF back annotation simulations.
  3. Take ownership of ATE pattern generation flow.
  4. Perform DFT verification.

Required Skills and Qualifications of the DFT Engineer:

  1. At least 5-7 years experience with DFT flows. Specifically:
    1. Experience with fault grading and coverage improvement.
    2. Experience running Synopsys Tetramax tool suite.
    3. TCL scripting for Synopsys tools.
  2. Experience with Python scripting (Perl if no Python).
  3. Experience with gate level and SDF simulations.

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