Interconnect FPGA/ASIC RTL Engineer

Cerebras is developing a radically new chip and system to dramatically accelerate deep learning applications. Our system runs training and inference workloads orders of magnitude faster than contemporary machines, fundamentally changing the way ML researchers work and pursue AI innovation.

We are innovating at every level of the stack – from chip, to microcode, to power delivery and cooling, to new algorithms and network architectures at the cutting edge of ML research. Our fully-integrated system delivers unprecedented performance because it is built from the ground up for deep learning workloads.

Cerebras is building a team of exceptional people to work together on big problems. Join us!

The Role

You will work with the hardware and software teams to design an FPGA/ASIC sub-system for IO interconnect.

  • Design the micro-architecture and protocols to meet the system performance requirements.
  • Write the RTL for multiple blocks within the design and work the verification team to test/debug the design.
  • Bring up the design in the lab in validate functionality and performance.

Skills & Qualifications

  • 3+ years relevant experience with bringing FPGA designs to production.
  • Experience with large scale FPGA technologies and tool flows, including timing closure, floorplanning, debugging techniques, etc.
  • In-depth knowledge of data center networking protocols, such as TCP/IP and RDMA preferred.
  • Experience with high-speed interfaces and bus protocols such as PCIe, 100G Ethernet, high speed memories such as DDR4 and/or HBM.


Our cozy and well-appointed headquarters are in the heart of Silicon Valley near downtown Los Altos, California.

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