Cerebras is building a team of exceptional people to work together on big problems. Join us!

Interconnect FPGA/ASIC RTL Engineer

You will work with the hardware and software teams to design an FPGA/ASIC sub-system for IO interconnect.

  • Design the micro-architecture and protocols to meet the system performance requirements.
  • Write the RTL for multiple blocks within the design and work the verification team to test/debug the design.
  • Bring up the design in the lab in validate functionality and performance.

Skills and Qualifications

  • 3+ years relevant experience with bringing FPGA designs to production.
  • Experience with large scale FPGA technologies and tool flows, including timing closure, floorplanning, debugging techniques, etc.
  • In-depth knowledge of data center networking protocols, such as TCP/IP and RDMA preferred.
  • Experience with high-speed interfaces and bus protocols such as PCIe, 100G Ethernet, high speed memories such as DDR4 and/or HBM.

Location

  • Our cozy and well-appointed headquarters are in the heart of Silicon Valley near downtown Los Altos, California.

Attach Resume (.doc or .pdf only — .docx NOT supported):