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Interconnect FPGA/ASIC RTL Engineer

You will work with the hardware and software teams to design an FPGA/ASIC sub-system for IO interconnect.

  • Design the micro-architecture and protocols to meet the system performance requirements.
  • Write the RTL for multiple blocks within the design and work the verification team to test/debug the design.
  • Bring up the design in the lab in validate functionality and performance.

Skills and Qualifications

  • Design the micro-architecture and protocols to meet the system performance requirements.
  • Write the RTL for multiple blocks within the design and work the verification team to test/debug the design.
  • Bring up the design in the lab in validate functionality and performance.

Location

  • Our cozy and well-appointed headquarters are in the heart of Silicon Valley near downtown Los Altos, California.

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