Design for Test Engineer

Cerebras has developed a radically new chip and system to dramatically accelerate deep learning applications. Our system runs training and inference workloads orders of magnitude faster than contemporary machines, fundamentally changing the way ML researchers work and pursue AI innovation.

We are innovating at every level of the stack – from chip, to microcode, to power delivery and cooling, to new algorithms and network architectures at the cutting edge of ML research. Our fully-integrated system delivers unprecedented performance because it is built from the ground up for deep learning workloads.

Cerebras is building a team of exceptional people to work together on big problems. Join us!

Responsibilities:

  1. Work on overcoming engineering challenges unique to Wafer Scale Engine (WSE) technology
  2. Be willing to innovate and create custom DFX solutions
  3. Work in close collaboration with the ASIC Design, Verification, Test Engineering and Back-end teams.
  4. Create and maintain Python and TCL based DFT tool flows.
  5. Generate ATPG patterns, create/run/debug gate and SDF back annotation simulations.
  6. Perform DFT verification

Required Qualifications:

  • A BS or MS in Electrical Engineering or related fields with 5+ years of DFT experience
  • Familiarity with Scan insertion, Scan compression, ATPG pattern generation and resolving test pattern and coverage issues
  • A good understanding of different ATPG fault models, including Stuck-AT, Transition, SDD and Cell-Aware fault models
  • Experience in MBIST insertion, simulation and debug on RTL and gates netlist
  • Experience JTAG and Boundary scan related 1149.1 and 1149.6 standards
  • Familiarity with logic design, handling Multiple clock domains and a good understanding of Verilog HDL
  • Experience in simulating and debugging simulation failures for ATPG and BIST patterns
  • Experience in Silicon Bring up of MBIST and ATPG patterns
  • Familiarity with ATE, Diagnosis, Fault isolation and Silicon failure Analysis
  • Ability to work with and support test and operations engineering for wafer test, burn-in and other production related activities
  • Very good scripting skills in Perl/Python and TCL
  • Excellent written and verbal communication skills in English

Preferred Qualifications

  • Familiar with Industry Standard ATPG and BIST tools from Synopsys and Mentor Graphics
  • Familiar with front-end design methodology including Formal Verification, Synthesis, Linting, and CDC.
  • Experience with PrimeTime based STA for test mode timing
  • Experience working Physical design engineers and Physical design flows
  • Experience working with EDA vendors and drive resolution of flow and tool related issues

Location

Los Altos, CA

Departments

  • ASIC:

Offices

  • Headquarters/Los Altos Office

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